Hierarchical Timing Analysis under the XBD0 Model

We propose a hierarchical timing analysis technique applicable to the XBD0 delay model, which is the underlying model for floating mode analysis and viability analysis. Given a hierarchical combinational circuit, the timing property of each leaf module is characterized first. Since this timing characterization step takes into account false paths in each module, a timing model constructed is more accurate than the one obtained by topological analysis. Arrival times at primary inputs of the entire circuit are then propagated through modules using the timing models of leaf modules. As far as the authors know, this is the first result which shows that hierarchical analysis is possible under state-of-the-art tight sensitization criteria while preserving accuracy. We demonstrate that loss of accuracy in using the hierarchical approach is very minimal in practice by showing that the hierarchical analysis gives the same delay as flat analysis for a cascaded carry-skip adder, which is known to contain many long false paths.